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    • 专利摘要:
    According to an example aspect of the present invention, there is provided an apparatus comprising a first processing core (210) configured to generate first control signals and to control a display (230) by providing the first control signals to the display (230) via a first display interface (212), a second processing core (220) configured to generate second control signals and to control the display (230) by providing the second control signals to the display (230) via a second display interface (222), and the first processing core (210) being further configured to cause the second processing core (220) to enter and leave a hibernation state based at least partly on a determination, by the first processing core (210), concerning an instruction from outside the apparatus.
    公开号:FI20206299A1
    申请号:FI20206299
    申请日:2020-12-14
    公开日:2021-06-21
    发明作者:Erik Lindman
    申请人:Amer Sports Digital Services Oy；
    IPC主号:
    专利说明:

    [0001] [0001] The present invention in general relates, for example, to implementing multi- — core or multi-chip embedded solutions.BACKGROUND OF INVENTION
    [0002] [0002] Embedded devices generally comprise objects that contain an embedded computing system, which may be enclosed by the object. The embedded computer system may be designed with a specific use in mind, or the embedded computer system may be at least in part general-purpose in the sense that a user may be enabled to install software in it. An embedded computer system may be based on a microcontroller or microprocessor CPU, for example.
    [0003] [0003] Embedded devices may comprise one or more processors, user interfaces and — displays, such that a user may interact with the device using the user interface. The user interface may comprise buttons, for example. An embedded device may comprise a connectivity function configured to communicate with a communications network, such as, for example, a wireless communications network. The embedded device may be enabled to receive from such a communications network information relating to, for example, a — current time and current time zone. N [0004] More complex embedded devices, such as cellular telephones, may allow a N user to install applications into a memory, such as, for example, a solid-state memory, 3 comprised in the device. Embedded devices are frequently resource-constrained when > compared to desktop or laptop computers. For example, memory capacity may be more E 25 — limited than in desktop or laptop computers, processor computational capacity may be 3 lower and energy may be available from a battery. The battery, which may be small, may
    [0005] [0005] Conserving battery power is a key task in designing embedded devices. A lower current usage enables longer time intervals in-between battery charging. For example, smartphones benefit greatly when they can survive an entire day before needing recharging, since users are thereby enabled to recharge their phones overnight, and enjoy uninterrupted use during the day.
    [0006] [0006] Battery resources may be conserved by throttling a processor clock frequency between a maximum clock frequency and a lower clock frequency, for example one half of the maximum clock frequency. Another way to conserve battery power is to cause a display of an embedded device to switch itself off then the device is not used, since displaying content on a display consumes energy in order to cause the display to emit light that humans can see.SUMMARY OF THE INVENTION
    [0007] [0007] The invention is defined by the features of the independent claims. Some specific embodiments are defined in the dependent claims.
    [0008] [0008] According to a first aspect of the present invention, there is provided an apparatus comprising a first processing core configured to generate first control signals and — to control a display by providing the first control signals to the display via a first display interface, a second processing core configured to generate second control signals and to control the display by providing the second control signals to the display via a second display interface, and the first processing core being further configured to cause the second processing core to enter and leave a hibernation state based at least partly on a — determination, by the first processing core, concerning an instruction from outside the apparatus. S [0009] Various embodiments of the first aspect may comprise at least one feature O . . N from the following bulleted list:
    [0010] [0010] According to a second aspect of the present invention, there is provided a method in an apparatus, comprising generating, by a first processing core, first control signals, controlling a display by providing the first control signals to the display via a first display interface, generating, by a second processing core, second control signals, controlling the display by providing the second control signals to the display via a second display interface, and causing the second processing core to enter and leave a hibernation state based at least partly on a determination, by the first processing core, concerning an instruction from outside the apparatus.
    [0011] [0011] Various embodiments of the first aspect may comprise at least one feature from the following bulleted list: e obtaining microphone data internally in the apparatus from a microphone comprised in the apparatus e the second processing core is electrically interfaced with at least one of: cellular communication circuitry, non-cellular wireless communication circuitry and a second wired communications port e the first processing core and the second processing core are both electrically interfaced with a shared random access memory e the method further comprises causing, by the first processing core, the second processing core to leave the hibernation state responsive to a determination that a a preconfigured spoken instruction has been recorded in the microphone data, the instruction from outside the apparatus comprising the preconfigured spoken Q instruction
    [0012] [0012] According to a third aspect of the present invention, there is provided an apparatus comprising at least one processing core and at least one memory including computer program code, the at least one memory and the computer program code being configured to, with the at least one processing core, cause the apparatus at least to generate, o by a first processing core, first control signals, control a display by providing the first IN control signals to the display via a first display interface, generate, by a second processing N core, second control signals, control the display by providing the second control signals to N the display via a second display interface, and cause the second processing core to enter = 25 and leave a hibernation state based at least partly on a determination, by the first a o processing core, concerning an instruction from outside the apparatus.O
    [0014] [0014] According to a fifth aspect of the present invention, there is provided a non- transitory computer readable non-transitory medium having stored thereon a set of computer readable instructions that, when executed by at least one processor, cause an apparatus to at least generate, by a first processing core, first control signals, control a display by providing the first control signals to the display via a first display interface, generate, by a second processing core, second control signals, control the display by providing the second control signals to the display via a second display interface, and cause the second processing core to enter and leave a hibernation state based at least partly on a determination, by the first processing core, concerning an instruction from outside the apparatus.
    [0015] [0015] According to a sixth aspect of the present invention, there is provided a computer program configured to cause a method in accordance with the second aspect to be performed, when run.
    [0016] [0016] At least some embodiments of the present invention find industrial — application in embedded multi-chip or multi-core and power usage optimization thereof.S BRIEF DESCRIPTION OF THE DRAWINGS
    [0019] [0019] FIGURE 3 illustrates a second example apparatus capable of supporting at least some embodiments of the present invention;
    [0020] [0020] FIGURE 4 illustrates an example diving information apparatus in accordance with at least some embodiments of the present invention;
    [0021] [0021] FIGURE 5 is a first flow chart of a first method in accordance with at least some embodiments of the present invention, and
    [0022] [0022] FIGURE 6 is a state transition diagram in accordance with at least some embodiments of the present invention.DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
    [0023] [0023] Furnishing an embedded device with two or more processor cores, at least some of which are enabled to control the display of the device, makes possible power savings where a less-capable processor core is configured to toggle a more capable processor core to and from a hibernation state. A hibernation state may comprise that a clock freguency of the more capable processing core is set to zero, for example. In a — hibernation state, in addition to, or alternatively to, setting the clock frequency of the more capable processing core to zero, a memory refresh rate of memory used by the more capable core may be set to zero. Alternatively to zero, a low non-zero freguency may be used for the clock freguency and/or the memory refresh freguency. In some embodiments, a more capable processing core may employ a higher-density memory technology, such as — double data rate, DDR, memory, and a less capable processing core may employ a lower- density memory technology, such as static random access memory, SRAM, memory. In a S hibernation state the hibernated processing core, or more generally processing unit, may be a powered off. Alternatively to a processor core, an entire processor may, in some 3 embodiments, be transitioned to a hibernation state. An advantage of hibernating an entire = 25 — processor is that circuitry in the processor outside the core is also hibernated, further : reducing current consumption.
    [0025] [0025] Device 110 is in the example of FIGURE 1 configured with a plurality of communication interfaces. A first communication interface enables device 110 to receive satellite positioning information from satellite constellation 140, via satellite link 114. Examples of suitable satellite positioning constellations include global positioning system, GPS, GLONASS, Beidou and the Galileo satellite positioning constellation.
    [0026] [0026] A second communications interface enables device 110 to communicate with a cellular communications system, such as for example a wideband code division multiple access, WCDMA, or long term evolution, LTE, network. A cellular link 112 may be configured to convey information between device 110 and base station 120. The cellular link 112 may be configured in accordance with the same cellular communications standard that both device 110 and base station 120 both support. Base station 120 may be comprised in a cellular radio access network that comprises a plurality of base stations. Base station 120 may be arranged to communicate with core network node 150 via connection 125. Core network node 150 may comprise a switch, mobility management entity or gateway, — for example. Core network node 150 may be arranged to communicate with a further network 170, such as for example the Internet, via connection 157.
    [0027] [0027] A third communications interface enables device 110 to communicate with a non-cellular communications system, such as for example a wireless local area network, WLAN, Bluetooth or worldwide interoperability for microwave access, WiMAX, system. — A further example is an inductive underwater communication interface. A non-cellular link 113 may be configured to convey information between device 110 and access point 130. The non-cellular link 113 may be configured in accordance with the same non-cellular technology that both device 110 and access point 130 both support. Access point 130 may S be arranged to communicate with gateway 160 via connection 136. Gateway 160 may be AN 25 arranged to communicate with further network 170 via connection 167. Each of I connections 125, 157, 136 and 167 may be wire-line or at least in part wireless. Not all of z these connections need to be of the same type. In certain embodiments, at least one of the > first communications interface, the second communications interface and the third communications interface is absent.
    [0029] [0029] In use, device 110 may use satellite positioning information from satellite constellation 140 to determine a geo-location of device 110. The geo-location may be determined in terms of coordinates, for example. Device 110 may be configured to present, on a display that may be comprised in device 110, a map with the determined geo-location of device 110 presented thereon. For example, device 110 may display a street or feature map of the surroundings, with a symbol denoting the current location of device 110 on the map. Providing a map with a current location of device 110 indicated thereon, and/or providing navigation instructions, may be referred to as a mapping service.
    [0030] [0030] In some embodiments, device 110 may provide connectivity services to a user, such as for example web browsing, instant messaging and/or email. Device 110 may be configured to provide connectivity service to its functions and/or applications, in some embodiments including enabling remote access to these functions and/or services over a — network, such as the Internet. Thus device 110 may be trackable over the Internet, for example. Such connectivity services may be run over bidirectional communication links, such as for example cellular link 112 and/or non-cellular link 113. In general, device 110 may provide a service, such as for example a mapping service or a connectivity service, to a user via a display.
    [0031] [0031] Device 110 may comprise two or more processing units. The two or more processing units may each comprise a processing core. Each processing unit may comprise one or multiple uniformal or heterogeneous processor cores and/or different volatile and S non-volatile memories. For example, device 110 may comprise a microprocessor with at N least one processing core, and a microcontroller with at least one processing core. The = 25 — processing cores needn't be of the same type, for example, a processing core in a = microcontroller may have more limited processing capability and/or a less capable memory = technology than a processing core comprised in a microprocessor. In some embodiments, a 2 single integrated circuit comprises two processing cores, a first one of which has lesser 3 processing capability and consumes less power, and a second one of which has greater S 30 processing capability and consumes more power. In general a first one of the two processing units may have lesser processing capability and consume less power, and a second one of the two processing units may have greater processing capability and consume more power. Each of the processing units may be enabled to control the display of device 110. The more capable processing unit may be configured to provide a richer visual experience via the display. The less capable processing unit may be configured to provide a reduced visual experience via the display. An example of a reduced visual experience is a reduced colour display mode, as opposed to a rich colour display mode. An another example of a reduced visual experience is one which is black-and-white. An example of a richer visual experience is one which uses colours. Colours may be represented with 16 bits or 24 bits, for example.
    [0032] [0032] Each of the two processing units may comprise a display interface configured — to communicate toward the display. For example, where the processing units comprise a microprocessor and a microcontroller, the microprocessor may comprise transceiver circuitry coupled to at least one metallic pin under the microprocessor, the at least one metallic pin being electrically coupled to an input interface of a display control device. The display control device, which may be comprised in the display, is configured to cause the — display to display information in dependence of electrical signals received in the display control device. Likewise the microcontroller in this example may comprise transceiver circuitry coupled to at least one metallic pin under the microcontroller, the at least one metallic pin being electrically coupled to an input interface of a display control device. The display control device may comprise two input interfaces, one coupled to each of the two processing units, or alternatively the display control device may comprise a single input interface into which both processing units are enabled to provide inputs via their respective display interfaces. Thus a display interface in a processing unit may comprise transceiver circuitry enabling the processing unit to transmit electrical signals toward the display.
    [0034] [0034] When transitioning into a hibernating state from an active state, the transitioning processing unit may store its context, at least in part, into a memory, such as for example a pseudostatic random access memory, PSRAM, SRAM, FLASH or ferroelectric RAM, FRAM. The context may comprise, for example, content of registers and/or addressing. When transitioning from a hibernated state using a context stored in memory, a processing unit may resume processing faster and/or from a position where the — processing unit was when it was hibernated. This way, a delay experienced by a user may be minimised. Alternative terms occasionally used for context include state and image. In a hibernating state, a clock frequency of the processing unit and/or an associated memory may be set to zero, meaning the processing unit is powered off and does not consume energy. Circuitry configured to provide an operating voltage to at least one processing unit may comprise a power management integrated circuit, PMIC, for example. Since device 110 comprises another processing unit, the hibernated processing unit may be powered completely off while maintaining usability of device 110.
    [0035] [0035] When transitioning from a hibernated state to an active state, the transitioning processing unit may have its clock frequency set to a non-zero value. The transitioning — processing unit may read a context from a memory, wherein the context may comprise a previously stored context, for example a context stored in connection with transitioning into the hibernated state, or the context may comprise a default state or context of the processing unit stored into the memory in the factory. The memory may comprise pseudostatic random access memory, SRAM, FLASH and/or FRAM, for example. The — memory used by the processing unit transitioning to and from the hibernated state may comprise DDR memory, for example.
    [0036] [0036] With one processing unit in a hibernation state, the non-hibernated processing unit may control device 110. For example, the non-hibernated processing unit S may control the display via the display interface comprised in the non-hibernated N 25 — processing unit. For example, where a less capable processing unit has caused a more + capable processing unit to transition to the hibernated state, the less capable processing unit z may provide a reduced user experience, for example, via at least in part, the display. An > example of a reduced user experience is a mapping experience with a reduced visual A experience comprising a black-and-white rendering of the mapping service. The reduced N 30 experience may be sufficient for the user to obtain a benefit from it, with the advantage N that battery power is conserved by hibernating the more capable processing unit. In some embodiments, a more capable processing unit, such as a microprocessor, may consume a milliampere of current when in a non-hibernated low-power state, while a less capable processing unit, such as a microcontroller, may consume only a microampere when in a non-hibernated low-power state. In non-hibernated states current consumption of processing units may be modified by setting an operating clock frequency to a value between a maximum clock frequency and a minimum non-zero clock frequency. In at least some embodiments, processing units, for example less capable processing units, may be configurable to power down for short periods, such as 10 or 15 microseconds, before being awakened. In the context of this document, this is not referred to as a hibernated state but an active low-power configuration. An average clock frequency calculated over a few such periods and the intervening active periods is a positive non-zero value. A more capable processing unit may be enabled to run the Android operating system, for example.
    [0037] [0037] Triggering events for causing a processing unit to transition to the hibernated state include a user indicating a non-reduced experience is no longer needed, a communication interface of the processing unit no longer being needed and device 110 not having been used for a predetermined length of time. An example indication that a non- — reduced experience is no longer needed is where the user deactivates a full version of an application, such as for example a mapping application. Triggering events for causing a processing unit to transition from the hibernated state to an active state may include a user indicating a non-reduced experience is needed, a communication interface of the processing unit being reguested and device 110 being interacted with after a period of inactivity. Alternatively or additionally, external events may be configured as triggering events, such as, for example, events based on sensors comprised in device 110. An example of such an external event is a clock-based event which is configured to occur at a preconfigured time of day, such as an alarm clock function, for example. In at least some S cmbodiments, the non-reduced cxpericnce comprises usc of a graphics mode the non- N 25 — hibernated processing unit cannot support, but the hibernated processing unit can support. = A graphics mode may comprise a combination of a resolution, colour depth and/or refresh = rate, for example.
    [0039] [0039] If the processing units reside in separate devices or housings, such as a wrist- top computer and a handheld or fixedly mounted display device for example, a bus may be implemented in a wireless fashion by using a wireless communication protocol. Radio transceiver units functionally connected to their respective processing units may thus perform the function of the bus, forming a personal area network, PAN. The wireless communication protocol may be one used for communication between computers, and/or between any remote sensors, such as a Bluetooth LE or the proprietary ANT+ protocol. These are using direct-seguence spread spectrum, DSSS, modulation technigues and an adaptive isochronous network configuration, respectively. Enabling descriptions of necessary hardware for various implementations for wireless links are available, for example, from the Texas Instrument®’s handbook “Wireless Connectivity” which includes IC circuits and related hardware configurations for protocols working in sub-1- and 2.4- GHz frequency bands, such as ANT™, Bluetooth®, Bluetooth® low energy, RFID/NFC, PurePath™ Wireless audio, ZigBee&, IEEE 802.15.4, ZigBee RF4CE, 6LoWPAN, Wi- FIG.
    [0040] [0040] In connection with hibernation, the PAN may be kept in operation by the non-hibernated processing unit, such that when hibernation ends, the processing unit leaving the hibernated mode may have access to the PAN without needing to re-establish it.
    [0041] [0041] In some embodiments, microphone data is used in determining, in a first processor, whether to trigger a second processor from hibernation. The first processor may be less capable and consume less energy than the second processor. The first processor may comprise a microcontroller and the second processor may comprise a microprocessor, S for example. The microphone data may be compared to reference data and/or preprocessed N 25 — to identify in the microphone data features enabling determination whether a spoken + instructions has been uttered and recorded into the microphone data. Alternatively or in z addition to a spoken instruction, an auditory control signal, such as a fire alarm or beep > signal, may be searched in the microphone data.
    [0043] [0043] In cases where a microphone is comprised in the apparatus, the microphone may in particular be enclosed inside a waterproof casing. While such a casing may prevent high-quality microphone data from being generated, it may allow for microphone quality to be generated that is of sufficient quality for the first processor to determine, whether the spoken instruction and/or auditory control signal is present.
    [0044] [0044] In some embodiments, the first processor is configured to process a notification that arrives in the apparatus, and to decide whether the second processor is — needed to handle the notification. The notification may relate to a multimedia message or incoming video call, for example. The notification may relate to a software update presented to the apparatus, wherein the first processor may cause the second processor to leave the hibernating state to handle the notification. The first processor may select, in dependence of the notification, an initial state into which the second processor starts from the hibernated state. For a duration of a software update, the second processor may cause the first processor to transition into a hibernated state.
    [0045] [0045] In general, an instruction from outside the apparatus may be received in the apparatus, and the first processor may responsively cause the second processor to leave the N hibernation state. The instruction from outside the apparatus may comprise, for example, 2 25 — the notification, the spoken instruction or the auditory control signal. <+ = [0046] FIGURE 2 illustrates a first example apparatus capable of supporting at least * some embodiments of the present invention. The illustrated apparatus comprises a 3 microcontroller 210 and a microprocessor 220. Microcontroller 210 may comprise, for N example, a Silabs EMF32 or a Renesas RL78 microcontroller, or similar. Microprocessor N 30 220 may comprise, for example, a Qualcomm Snapdragon processor or an ARM Cortex- based processor. Microcontroller 210 and microprocessor 220 are in the example of FIGURE 2 communicatively coupled with an inter-core interface, which may comprise, for example, a serial or a parallel communication interface. More generally an interface disposed between microcontroller 210 and microprocessor 220 may be considered an inter- processing unit interface.
    [0047] [0047] Microcontroller 210 is communicatively coupled, in the illustrated example, with a buzzer 270, a universal serial bus, USB, interface 280, a pressure sensor 290, an acceleration sensor 2100, a gyroscope 2110, a magnetometer 2120, satellite positioning circuitry 2130, a Bluetooth interface 2140, user interface buttons 2150 and a touch interface 2160. Pressure sensor 290 may comprise an atmospheric pressure sensor, for example.
    [0048] [0048] Microprocessor 220 is communicatively coupled with an optional cellular interface 240, a non-cellular interface 250 and a USB interface 260. Microprocessor 220 is further communicatively coupled, via microprocessor display interface 222, with display
    [0049] [0049] Microcontroller 210 may be configured to determine whether triggering events occur, wherein responsive to the triggering events microcontroller 210 may be configured to cause microprocessor 220 to transition into and out of the hibernating state — described above. When microprocessor 220 is in the hibernating state, microcontroller 210 may control display 230 via microcontroller display interface 222. Microcontroller 210 may thus provide, when microprocessor 220 is hibernated, for example, a reduced experience to a user via display 230.O
    [0051] [0051] In various embodiments, at least two elements illustrated in FIGURE 2 may be integrated on a same integrated circuit. For example, microprocessor 220 and microcontroller 210 may be disposed as processing cores in a same integrated circuit. Where this is the case, for example, cellular interface 240 may be a cellular interface of this integrated circuit, comprised in this integrated circuit, with cellular interface 240 being controllable by microprocessor 220 but not by microcontroller 210. In other words, individual hardware features of the integrated circuit may be controllable by one of microcontroller 210 and microprocessor 220, but not both. On the other hand, some hardware features may be controllable by either processing unit. For example, USB interface 260 and USB interface 280 may be in such an integrated embodiment one and the same USB interface of the integrated circuit, controllable by either processing core.
    [0052] [0052] In FIGURE 2 are further illustrated memory 2170 and memory 2180.
    [0053] [0053] FIGURE 3 illustrates a second example apparatus capable of supporting at least some embodiments of the present invention.
    [0054] [0054] Illustrated is device 300, which may comprise, for example, an embedded device 110 of FIGURE 1. Comprised in device 300 is processor 310, which may comprise, for example, a single- or multi-core processor wherein a single-core processor comprises N one processing core and a multi-core processor comprises more than one processing core. 2 Processor 310 may correspond to the structure illustrated in FIGURE 2, with the exception I 25 — of display 230, for example. Processor 310 may comprise more than one processor or = processing unit. Processor 310 may comprise at least one application-specific integrated * circuit, ASIC. Processor 310 may comprise at least one field-programmable gate array, FPGA. Processor 310 may be means for performing method steps in device 300. Processor S 310 may be configured, at least in part by computer instructions, to perform actions.N
    [0055] [0055] Device 300 may comprise memory 320. Memory 320 may comprise random- access memory and/or permanent memory. Memory 320 may comprise volatile and/or non-volatile memory. Memory 320 may comprise at least one RAM chip. Memory 320 may comprise magnetic, optical and/or holographic memory, for example. Memory 320 may be at least in part accessible to processor 310. Memory 320 may be means for storing information. Memory 320 may comprise computer instructions that processor 310 is configured to execute. When computer instructions configured to cause processor 310 to perform certain actions are stored in memory 320, and device 300 overall is configured to run under the direction of processor 310 using computer instructions from memory 320, processor 310 and/or its at least one processing core may be considered to be configured to perform said certain actions. Memory 320 may be at least in part comprised in processor
    [0056] [0056] Device 300 may comprise a transmitter 330. Device 300 may comprise a receiver 340. Transmitter 330 and receiver 340 may be configured to transmit and receive, respectively, information in accordance with at least one cellular or non-cellular standard.
    [0057] [0057] Device 300 may comprise a near-field communication, NFC, transceiver 350.
    [0059] [0059] Device 300 may comprise or be arranged to accept a user identity module
    [0060] [0060] Processor 310 may be furnished with a transmitter arranged to output information from processor 310, via electrical leads internal to device 300, to other devices comprised in device 300. Such a transmitter may comprise a serial bus transmitter arranged to, for example, output information via at least one electrical lead to memory 320 for storage therein. Alternatively to a serial bus, the transmitter may comprise a parallel bus transmitter. Likewise processor 310 may comprise a receiver arranged to receive information in processor 310, via electrical leads internal to device 300, from other devices comprised in device 300. Such a receiver may comprise a serial bus receiver arranged to, for example, receive information via at least one electrical lead from receiver 340 for processing in processor 310. Alternatively to a serial bus, the receiver may comprise a parallel bus receiver.
    [0061] [0061] Device 300 may comprise further devices not illustrated in FIGURE 3. For example, where device 300 comprises a smartphone, it may comprise at least one digital S camera. Some devices 300 may comprise a back-facing camera and a front-facing camera, N wherein the back-facing camera may be intended for digital photography and the front- = 25 facing camera for video telephony. Device 300 may comprise a fingerprint sensor arranged J to authenticate, at least in part, a user of device 300. In some embodiments, device 300 = lacks at least one device described above. For example, some devices 300 may lack a NFC 2 transceiver 350 and/or user identity module 370.
    [0063] [0063] In general, there is provided a diving information apparatus, which comprises first and second processing cores. The first processing core, which may have lower processing capability and lower power usage than the second processing core, may be configured to maintain dive information during a dive. A dive may comprise a dive under water, that is, a period of time when a user is submerged. Having a processing core with a lower power consumption maintain the dive information increases the time the apparatus can maintain the dive information, as the second processing core may be kept, for the most part, in a hibernation state, as will be described herein. The first processing core may control a display, which may be comprised in the diving information apparatus, to display the dive information and/or indications derived from the dive information.
    [0064] [0064] As the dive information may comprise, for example, at least one of a remaining time before ascent toward the surface should begin, decompression data, safety stop data, a remaining amount of air, any possible messages from other divers and depth as a function of time, the dive information is safety critical for a diver. As such, since safety critical information is being handled, a redundant information management system is of interest. Redundancy in the present dive information apparatus is provided by the second processing core, which may be configured to switch from the hibernation state to an active state periodically, for example at constant periods, to verify the dive information is correct. For example, the second processing core may be configured to check gas levels have S progressed in a credible fashion during the dive, there are no sudden jumps in diving depth, N 25 — and the remaining time develops consistently with other aspects of the dive information. In + other words, the second processing core may verify the dive information has not become z corrupted due to bit errors, memory corruption or bugs in the first processing core. In case > the dive information is verified as correct, the second processing core may return to the A hibernation state as a response to such verification.
    [0066] [0066] The dive information may be kept in at least one non-volatile memory, as will be discussed herein below in connection with FIGURE 4.
    [0067] [0067] The first processing core may be configured to re-boot in case an error occurs, and resume maintaining the dive information from the non-volatile memory. As the memory is non-volatile, it will keep the dive information over the re-boot. In general, the dive information may be stored in the form of plural time series, enabling re-constructing — the dive by observing how variables comprised in the dive information develop as a function of time. For example, one time series may be a time series of diving depth values, another time series may be a time series of remaining air values, and so on.
    [0068] [0068] The second processing core may be configured to, as a response to the verifying of the dive information indicating the dive information is corrupt, cause the first — processing core to stop maintaining the dive information. This may comprise setting the first processing core into an inactive state. The second processing core may then assume the role of maintaining the dive information for the remainder of the dive. The second processing core may further be configured to attempt to repair the dive information, for example by determining which variable is unreliable, for example due to an unnatural — sudden change in its value, and re-obtain that variable from another source. The second processing core may be configured to provide an indication to the diver, of which dive information may have become unreliable. The second processing core may be configured S to cease providing to the display any indication of specific variables of the dive N information which have been determined to be unreliable or potentially unreliable. This = 25 — would maintain the benefit that the diver can have confidence in the information he is = provided with, and he may abort the dive as safely as possible.E
    [0069] [0069] In some embodiments, the second processing core is triggered from the 3 hibernation state to the active state as a response to a determination that ascent toward the N surface should begin soon, for example, within one minute or within three minutes. Such a N 30 determination may be reached based on the dive information, for example. The reason the second processing core may be started in this situation, is that the second processing core may be capable of presenting to the display a visually more engaging indication that ascent should begin soon. As the first processing core has lower capability, it may only be capable of providing a monochrome and/or slowly updating display mode, whereas the second processing core may be able to provide a more colourful and/or animated display, suitable for conveying a warning that catches the attention of the user.
    [0070] [0070] FIGURE 4 illustrates an example diving information apparatus in accordance with at least some embodiments of the present invention. Illustrated are two processing cores, CORE 1 and CORE 2. The cores may be microcontroller cores, for example, or one of them may be a microcontroller core and the other a microprocessor core. One of the cores may be more capable, and consume more power, than the other one. Thus, for example, a first microcontroller core may be more power-hungry than another microcontroller core in case both COREI and CORE2 are microcontroller cores. COREI and CORE2 may be comprised in a same integrated circuit, or they may be comprised in distinct integrated circuits, such as microcontroller(s) or microprocessor(s).
    [0071] [0071] The system of FIGURE 4 further comprises two non-volatile memories, one for each processing core, and a replication mechanism configured to replicate dive information between the non-volatile memories. In effect, where the first processing core COREI maintains the dive information in non-volatile memory 1, the replication mechanism maintains an identical dive information in non-volatile memory 2. The replication mechanism may be external to the first processing core and the second processing core, whereby in case one of the processing cored develops a fault, the replication will continue. Alternatively to two non-volatile memories, the diving information apparatus may comprise a single non-volatile memory, such that both processing cores may access the single non-volatile memory. The non-volatile memories S may be of different types, such as, produced by different manufactures, and/or based on N 25 — different underlying technology, such as NAND and NOR flash. The different types make I it less likely, that both non-volatile memories fail at the same time. The non-volatile z memories may be external to the processing cores and/or the integrated circuit(s) where the > processing cores are comprised. In some embodiments, the non-volatile memory or non- A volatile memories are comprised in a same integrated circuit as both of the processing N 30 cores, in embodiments where the processing cores are comprised in the same integrated N circuit.
    [0072] [0072] Optionally, second processing core CORE2 may have an interface with non- volatile memory 1, and first processing core CORE 1 may have an interface with non- volatile memory 2. These optional interfaces enable checking the replication mechanism works properly.
    [0073] [0073] In general, the diving information apparatus may comprise two pressure sensors, a barometric pressure sensor and a second pressure sensor configured to determine, from water pressure, a water depth of the diving information apparatus. The barometric pressure sensor may be configured to measure atmospheric pressure and pressure of water up to a depth of ten or twenty meters, for example. The second pressure sensor may be configured to measure water pressure up to 40, 50, 60, 80 or 100 meters, for example. In detail, there may be a region of depth overlap of active ranges of the pressure sensors, for example between water surface and a depth of ten or twenty meters, where both pressure sensors are enabled to produce a pressure reading.
    [0074] [0074] The two pressure sensors may be integrated on a same chip, or they may be disposed in the diving information apparatus as distinct components.
    [0075] [0075] — The first and second processing cores may both be capable of receiving input from both of the two pressure sensors. When the diving information apparatus is in the region of depth overlap, one or both of the processing cores may compare pressure readings from the two pressure sensors, and responsive to determining the pressure sensors — produce inconsistent information indicating two different depths, a warning signal may be provided to the user that depth information has become unreliable. In other words, a warning may be provided to the user as a response to determining the two pressure sensors S provide pressure data inconsistent with each other .The user may then choose to abort the N dive. This may occur in case one of the pressure sensors malfunctions during a dive, = 25 — creating what may become a dangerous situation. For example, descending deeper than the = region of depth overlap may be avoided by aborting the dive when still in the region of E depth overlap. 3 [0076] In case the user descends toward the lower bound of the region of depth N overlap, the diving information apparatus may be configured to close off the barometric N 30 pressure sensor from the water to prevent it from being damaged by high pressure. On the other hand, additionally or alternatively, when the diver approaches the region of depth overlap from below, the diving information apparatus may be configured to expose the barometric pressure sensor to the water pressure once the device re-enters the region of depth overlap. A further mechanism to protect the barometric pressure sensor is to decouple it from an electrical current source when descending toward the lower bound of the region of overlap. The decoupling may be performed without the closing off and/or the exposing mentioned in this paragraph, or it may be performed in combination with this closing off and/or this exposing.
    [0077] [0077] FIGURE 5 is a first flow chart of a first method in accordance with at least some embodiments of the present invention. The phases of the illustrated method may be performed in device 110 of FIGURE 1, or in the apparatus of FIGURE 2, for example.
    [0078] [0078] Phase 510 comprises maintaining, by a first processing core, during a dive, dive information which concerns progress of the dive. Phase 520 comprises generating, by the first processing core, first control signals and controlling, by the first processing core, a display by providing the first control signals to the display via a display interface. Phase 530 comprises repeatedly switching, by a second processing core, from a hibernation state to an active state during the dive, verifying, by the second processing core, the dive information and switching the second processing core back to the hibernation state responsive to the dive information being verified as correct. Phase 540 comprises the dive information is stored in at least one non-volatile memory comprised in the diving information apparatus.
    [0079] [0079] FIGURE 6 is a state transition diagram in accordance with at least some embodiments of the present invention.
    [0080] [0080] PUI corresponds to processing unit 1, for example, a less capable processing N unit. PU2 corresponds to processing unit 2, for example, a more capable processing unit.
    [0082] [0082] In addition to, or alternatively to, a power-off state PUI and/or PU2 may have an intermediate low-power state from which it may be transitioned to an active state faster than from a complete power-off state. For example, a processing unit may be set to such an intermediate low-power state before being set to a power-off state. In case the processing unit is needed soon afterward, it may be caused to transition back to the power- up state. If no need for the processing unit is identified within a preconfigured time, the processing unit may be caused to transition from the intermediate low-power state to a power-off state.
    [0083] [0083] Arrow 610 denotes a transition from state “10” to state “11”, in other words, a transition where PU2 is transitioned from the hibernated state to an active state, for example, a state where its clock frequency is non-zero. PUI may cause the transition denoted by arrow 610 to occur, for example, responsive to a triggering event. In state *11”, the device may be able to offer a richer experience, at the cost of faster battery power consumption.
    [0084] [0084] Arrow 620 denotes a transition from state “11” to state “10”, in other words, a transition where PU2 is transitioned from an active state to the hibernated state. PUI may cause the transition denoted by arrow 620 to occur, for example, responsive to a triggering event.
    [0085] [0085] It is to be understood that the embodiments of the invention disclosed are not — limited to the particular structures, process steps, or materials disclosed herein, but are extended to eguivalents thereof as would be recognized by those ordinarily skilled in the relevant arts. It should also be understood that terminology employed herein is used for ES the purpose of describing particular embodiments only and is not intended to be limiting.
    [0087] [0087] As used herein, a plurality of items, structural elements, compositional elements, and/or materials may be presented in a common list for convenience. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on their presentation in a common group without indications to the contrary. In addition, various embodiments and example of the present invention may be referred to herein along with alternatives for the various components thereof. It is understood that such embodiments, examples, and alternatives are not to be construed as de facto equivalents of one another, but are to be considered as separate and autonomous representations of the present invention.
    [0088] [0088] Furthermore, described features, structures, or characteristics may be combined in any suitable or technically feasible manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of lengths, widths, shapes, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, — materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
    [0089] [0089] While the forgoing examples are illustrative of the principles of the present invention in one or more particular applications, it will be apparent to those of ordinary skill in the art that numerous modifications in form, usage and details of implementation — can be made without the exercise of inventive faculty, and without departing from the principles and concepts of the invention. Accordingly, it is not intended that the invention be limited, except as by the claims set forth below.ONON
    N +
    I a a oO
    N ©ONON
    权利要求:
    Claims (24)
    [1] 1. A diving information apparatus comprising: a first processing core configured to maintain, during a dive, dive information which concerns progress of the dive, to generate first control signals and to control a display by providing the first control signals to the display via a display interface; a second processing core configured to repeatedly switch from a hibernation state to an active state during the dive, to verify the dive information and to switch back to the hibernation state responsive to the dive information being verified as correct, and wherein the dive information is stored in at least one non-volatile memory comprised in the diving information apparatus.
    [2] — 2. The diving information apparatus according claim 1, wherein the first processing core uses less power when in an active mode, than the second processing core when the second processing core is not in the hibernation state.
    [3] 3. The diving information apparatus according claim 2, wherein the first processing core is comprised in a microcontroller and the second processing core is comprised in a microprocessor, the microcontroller being external to the microprocessor and the
    O N microprocessor being external to the microcontroller.
    N =
    [4] 4. The diving information apparatus according to any of claims 1 - 3, further comprising = . . . . . . — two pressure sensors, wherein the first processing core is configured to receive pressure E sensor data from both pressure sensors when the diving information apparatus is within a ox 25 — region of depth overlap between active ranges of the two pressure sensors, and to provide a N . ko . Q warning to the user as a response to determining the two pressure sensors provide pressure N . . . S data inconsistent with each other.
    [5] 5. The diving information apparatus according to any of claims 1 - 4, wherein the dive information comprises at least one of: a remaining time before ascent should begin, a remaining amount of air, messages from other divers and depth as a function of time.
    [6] 6. The diving information apparatus according to any of claims 1 - 5, wherein the first — processing core is configured to store the dive information in a first non-volatile memory and the second processing core is configured to access the dive information in a second non-volatile memory, the first and second non-volatile memories being arranged to replicate the dive information.
    [7] 7. The diving information apparatus according to claim 6, wherein the first and second non-volatile memories are not of a same type.
    [8] 8. The diving information apparatus according to any of claims 1 - 7, wherein the first processing core is configured to re-boot as a response to an error state occurring during the dive, and to resume maintaining the dive information after the re-boot.
    [9] 9. The diving information apparatus according to any of claims 1 - 8, wherein the second processing core is configured to cause the first processing core to stop maintaining the dive information as a response to the dive information being verified as incorrect.
    [10] 10. The diving information apparatus according to claim 9, wherein the second processing core is configured to maintain the dive information for a remainder of the dive subsequent to stopping the first processing core from maintaining the dive information. —
    [11] 11. The diving information apparatus according to any of claims 1 - 10, wherein the at least one non-volatile memory is external to the first processing core and the second processing
    O N core.
    N —
    [12] 12. The diving information apparatus according to any of claims 1 - 11, wherein the diving = . . . . . . — information apparatus is further configured to trigger the second processing core from the E 25 — hibernation state to the active state as a response to a determination that less than a 2 predetermined length of time remains before ascent toward a surface should start, and to N . . . . . © use the second processing core to provide graphical warning to the user, the graphical
    N N . . . . . S warning being of a type the first processing core cannot provide.
    [13] 13. A method in a diving information apparatus, comprising:
    maintaining, by a first processing core, during a dive, dive information which concerns progress of the dive, generating, by the first processing core, first control signals and controlling, by the first processing core, a display by providing the first control signals to the display via a display interface; repeatedly switching, by a second processing core, from a hibernation state to an active state during the dive, verifying, by the second processing core, the dive information and switching the second processing core back to the hibernation state responsive to the dive information being verified as correct, and wherein the dive information is stored in at least one non-volatile memory comprised in the diving information apparatus.
    [14] 14. The method according claim 13, wherein the first processing core uses less power when in an active mode, than the second processing core when the second processing core is not in the hibernation state.
    [15] 15. The method according claim 14, wherein the first processing core is comprised in a microcontroller and the second processing core is comprised in a microprocessor, the microcontroller being external to the microprocessor and the microprocessor being external to the microcontroller.
    [16] 16. A method according to any of claims 13 - 15, wherein the diving information apparatus comprises two pressure sensors, wherein the first processing core receives pressure sensor — data from both pressure sensors when the diving information apparatus is within a region of depth overlap between active ranges of the two pressure sensors, and provides a warning S to the user as a response to determining the two pressure sensors provide pressure data N inconsistent with each other.
    N 3
    [17] 17. The method according to any of claims 13 - 16, wherein the dive information = 25 comprises at least one of: a remaining time before ascent should begin, a remaining a amount of air, messages from other divers and depth as a function of time. 2 ©
    [18] 18. The method according to any of claims 13 - 17, comprising storing, by the first O processing core, the dive information in a first non-volatile memory and accessing, by the second processing core, the dive information in a second non-volatile memory, the first and second non-volatile memories being arranged to replicate the dive information.
    [19] 19. The method according to claim 18, wherein the first and second non-volatile memories are not of a same type.
    [20] 20. The method according to any of claims 13 - 19, further comprising re-booting the first processing core as a response to an error state occurring during the dive, and resuming maintaining the dive information by the first processing core after the re-boot.
    [21] 21. The method according to any of claims 13 - 20, further comprising causing, by the second processing core, the first processing core to stop maintaining the dive information as a response to the dive information being verified as incorrect.
    [22] 22. The method according to claim 21, wherein the second processing core maintains the — dive information for a remainder of the dive subsequent to stopping the first processing core from maintaining the dive information.
    [23] 23. The method according to any of claims 13 - 22, wherein the at least one non-volatile memory is external to the first processing core and the second processing core.
    [24] 24. A non-transitory computer readable non-transitory medium having stored thereon a set — of computer readable instructions that, when executed by at least one processor, cause a diving information apparatus to at least: maintain, by a first processing core, during a dive, dive information which concerns progress of the dive, generate, by the first processing core, first control signals and control, by the first processing core, a display by providing the first control signals to the display via a display interface; o repeatedly switch, by a second processing core, from a hibernation state O . . . . . . N to an active state during the dive, verify, by the second processing core, the dive — information and switch the second processing core back to the hibernation state — responsive to the dive information being verified as correct, and
    I = wherein the dive information is stored in at least one non-volatile o 2 memory comprised in the diving information apparatus. ©
    O
    N
    O
    N
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US5503145A|1992-06-19|1996-04-02|Clough; Stuart|Computer-controlling life support system and method for mixed-gas diving|
    US5457284A|1993-05-24|1995-10-10|Dacor Corporation|Interactive dive computer|
    GB2404593A|2003-07-03|2005-02-09|Alexander Roger Deas|Control electronics system for rebreather|
    JP5811469B2|2010-03-05|2015-11-11|ミネトロニクス インコーポレイティド|Portable controller with integrated power supply for mechanical circulation assist system|
    US20190367143A1|2012-03-28|2019-12-05|Marine Depth Control Engineering, Llc|Smart buoyancy assistant|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US16/722,038|US20200141827A1|2016-10-17|2019-12-20|Embedded computing device|
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